The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 2020
Filed:
Nov. 08, 2019
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
Kallol Mazumder, Plano, TX (US);
William O'Leary, Plano, TX (US);
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/16 (2006.01); G11C 29/00 (2006.01); H03K 19/173 (2006.01); G11C 8/10 (2006.01); G11C 7/22 (2006.01); G11C 8/08 (2006.01); G06F 11/267 (2006.01); G11C 7/10 (2006.01); G11C 8/06 (2006.01); G11C 29/46 (2006.01);
U.S. Cl.
CPC ...
G11C 29/16 (2013.01); G06F 11/267 (2013.01); G11C 7/109 (2013.01); G11C 7/1045 (2013.01); G11C 7/22 (2013.01); G11C 8/08 (2013.01); G11C 8/10 (2013.01); G11C 29/00 (2013.01); H03K 19/1737 (2013.01); G11C 8/06 (2013.01); G11C 29/46 (2013.01);
Abstract
Apparatuses and methods for nested mode registers to extend mode register functionality are disclosed. An example apparatus comprises a mode register configured to store address information and write data, a plurality of nested mode registers coupled to the mode register and configured to store the write data, and a decoder circuit coupled to the mode register and the plurality of nested mode registers and configured to selectively enable a nested mode register of the plurality of nested mode registers to store the write data based, at least in part, on the address information.