The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Sep. 25, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

William A. Lendvay, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); G06F 3/0604 (2013.01); G06F 3/068 (2013.01); G06F 3/0659 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0016 (2013.01);
Abstract

Systems, apparatuses, and methods related to an isolation circuit in a memory module are described. A dual-in line memory module (DIMM), for example, may include an isolation circuit to isolate components from one another in certain operating modes or phases of module operation. The isolation circuit may, for instance, isolate one integrated circuit (e.g., an electrically erasable read-only memory (EEPROM)) that includes serial presence detect (SPD) information from a controller (e.g., a field programmable gate array (FPGA)) if the controller is not energized. The isolation circuit may be employed in a non-volatile DIMM (NVDIMM), and an integrated circuit of the NVDIMM (e.g., an SPD EEPROM) may be isolated from an FPGA of the NVDIMM while the NVDIMM is de-energized. The isolation circuit may be employed in other examples to isolate or couple, or both, different components from or to one another.


Find Patent Forward Citations

Loading…