The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Nov. 26, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Prasoonkumar Surti, Folsom, CA (US);

David Cowperthwaite, Portland, OR (US);

Abhishek R. Appu, El Dorado Hills, CA (US);

Joydeep Ray, Folsom, CA (US);

Vasanth Ranganathan, El Dorado Hills, CA (US);

Altug Koker, El Dorado Hills, CA (US);

Balaji Vembu, Folsom, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 1/329 (2019.01);
U.S. Cl.
CPC ...
G06F 9/5088 (2013.01); G06F 1/329 (2013.01); G06F 2206/1004 (2013.01); G06F 2212/251 (2013.01);
Abstract

A mechanism is described for facilitating localized load-balancing for processors in computing devices. A method of embodiments, as described herein, includes facilitating hosting, at a processor of a computing device, a local load-balancing mechanism. The method may further include monitoring balancing of loads at the processor and serving as a local scheduler to maintain de-centralized load-balancing at the processor and between the processor and other one or more processors.


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