The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 22, 2020
Filed:
Jun. 28, 2019
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Jeremy Walker, San Jose, CA (US);
Hiu Ming Lam, San Jose, CA (US);
Mohammad Ranjbar, Los Altos, CA (US);
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 9/00 (2006.01); H04L 7/033 (2006.01); G06F 1/08 (2006.01); G06F 1/10 (2006.01); G11C 7/22 (2006.01); G11C 8/18 (2006.01); G11C 27/02 (2006.01);
U.S. Cl.
CPC ...
H04L 7/033 (2013.01); G06F 1/08 (2013.01); G06F 1/10 (2013.01); G11C 7/222 (2013.01); G11C 8/18 (2013.01); G11C 27/02 (2013.01); H03M 9/00 (2013.01);
Abstract
According to certain aspects, the present embodiments are directed generally to data communication systems, and more particularly to generating multi-phase clocks in a SerDes system. Embodiments provide SerDes components and methods that are capable of generating multiple different sampling frequencies for parallelizing serial data from a single high speed clock. These and other embodiments can be implemented with circuits that are relatively small and low-power as compared to conventional approaches.