Memory circuitry having a pair of immediately-adjacent memory arrays having space laterally-there-between that has a conductive interconnect in the space

Abstract

In some embodiments, memory circuitry comprises a pair of immediately-adjacent memory arrays having space laterally there-between. The memory arrays individually comprise memory cells individually having upper and lower elevationally-extending transistors and a capacitor elevationally there-between. The memory arrays comprise individual rows that (a) have an upper access line above and directly electrically coupled to a lower access line, and (b) are directly electrically coupled to one another across the space. The lower access line in one of the rows extends across the space from one of the memory arrays to the other of the memory arrays. Another of the rows comprises a conductive interconnect extending across a portion of the space. The conductive interconnect includes a horizontally-extending portion within the space that is laterally offset from the another row. Other aspects and implementations are disclosed.