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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10872823 B1

PDFFull Text
Date of Patent:
Dec. 22, 2020

Filed:

Aug. 31, 2017

Device integrated with junction field effect transistor and method for manufacturing the same

Applicant:

Csmc Technologies Fab2 Co., Ltd., Jiangsu, CN;

Inventors:

Yan Gu, Jiangsu, CN;

Shikang Cheng, Jiangsu, CN;

Sen Zhang, Jiangsu, CN;

Assignee:

CSMC TECHNOLOGIES FAB2 CO., LTD., Wuxi New District, CN;

Attorney:

Polsinelli PC

Primary Examiner:

Tucker J Wright

Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/265 (2006.01); H01L 21/306 (2006.01); H01L 27/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/808 (2006.01); H01L 27/085 (2006.01); H01L 21/8232 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823487 (2013.01); H01L 21/26513 (2013.01); H01L 21/30604 (2013.01); H01L 21/8232 (2013.01); H01L 27/0617 (2013.01); H01L 27/085 (2013.01); H01L 29/0843 (2013.01); H01L 29/0865 (2013.01); H01L 29/1095 (2013.01); H01L 29/401 (2013.01); H01L 29/45 (2013.01); H01L 29/66712 (2013.01); H01L 29/66909 (2013.01); H01L 29/78 (2013.01); H01L 29/7803 (2013.01); H01L 29/8083 (2013.01);
Abstract

A device integrated with JFET, the device is divided into a JFET region and a power device region, and the device includes: a drain () with a first conduction type; and a first conduction type region disposed on a front surface of the drain (); the JFET region includes: a first well () with a second conduction type and formed in the first conduction type region; a second well () with a second conduction type and formed in the first conduction type region; a JFET source () with the first conduction type; a metal electrode formed on the JFET source (), which is in contact with the JFET source (); and a second conduction type buried layer () formed under the JFET source () and the second well ().

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