The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2020

Filed:

Dec. 10, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jin Ho Park, Seoul, KR;

Sae Il Son, Suwon-si, KR;

Hye Jun Jin, Seongnam-si, KR;

Yun-Won Ha, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76808 (2013.01); H01L 21/76816 (2013.01); H01L 21/76826 (2013.01); H01L 21/76831 (2013.01); H01L 23/5226 (2013.01);
Abstract

An etch stop layer is formed on a lower wiring. An interlayer insulating film covers the lower wiring and the etch stop layer. A via exposes an upper surface of the etch stop layer, in the interlayer insulating film. A first filler is formed in the via. The first filler is etched to a first filler pattern. A second filler is formed on the first filler pattern and is etched to a second filler pattern. A trench is formed by etching the interlayer insulating film. The first and second filler patterns are etched during the forming of the trench to form a residual filler pattern. The residual filler pattern and the etch stop layer are removed and a wiring structure is formed electrically connected to the lower wiring. The via includes lower and upper portions and the trench includes the upper portion of the via.


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