The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2020

Filed:

Oct. 10, 2018
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Arnold Jean Marie Gustave Ginetti, Antibes, FR;

Jean-Noel Pic, Valbonne, FR;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 30/398 (2020.01); G06F 111/02 (2020.01); G06F 111/20 (2020.01); G06F 113/18 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 2111/02 (2020.01); G06F 2111/20 (2020.01); G06F 2113/18 (2020.01);
Abstract

Disclosed are methods, systems, and articles of manufacture for reducing interferences and disturbances in a multi-fabric electronic design. These techniques identify connectivity for an electronic design that includes design data in multiple design fabrics. One or more interference modules are executed to detect a loop in the electronic design with at least the connectivity. These techniques further execute the one or more interference reduction modules to determine at least one critical circuit component upon which the loop exerts a negative impact. One or more remedial actions are then triggered to reduce or eliminate the negative impact on the critical circuit component design.


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