The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 15, 2020
Filed:
May. 08, 2020
Xilinx, Inc., San Jose, CA (US);
Didem Z. Turker Melek, San Jose, CA (US);
Mayank Raj, San Jose, CA (US);
Adebabay M. Bekele, San Jose, CA (US);
Parag Upadhyaya, Los gatos, CA (US);
Yohan Frans, Palo Alto, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
Apparatus and associated methods relate to implementing an analog auxiliary clock and data recovery (CDR) path to provide a high bandwidth CDR in a transceiver that supports both PAM4 and NRZ signaling. In an illustrative example, the auxiliary CDR path may include a phase-frequency detector (PFD)-based phase-locked loop (PLL) and a phase detector (PD)-based PLL. When the PFD-based PLL is locked to a reference clock signal of the transceiver, the PFD-based PLL may be then disabled and the PD-based PLL may be then enabled. Implementing the auxiliary CDR path may advantageously enable the transceiver to implement much larger parts per million (ppm) acquisition and tracking, and thus enable the transceiver to advantageously support new standards such as Peripheral Component Interconnect Express (PCIe) 5.0 and PCIe 6.0, for example.