The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Jul. 01, 2019
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/356 (2006.01); H03K 3/037 (2006.01); H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
H03K 3/356173 (2013.01); H03K 3/0372 (2013.01); H03K 3/0375 (2013.01); H03K 19/003 (2013.01);
Abstract

Synchronizer circuits having controllable metastability are provided, one of which includes: a first flip-flop circuit comprising a first master latch connected in series with a first slave latch; and a second flip-flop circuit comprising a second master latch connected in series with a second slave latch, wherein an output of the first flip-flop circuit is connected to an input of the second flip-flop circuit, at least a portion of the first flip-flop circuit is implemented in a first PWell isolated by an underlying a deep isolation NWell, at least a portion of the first flip-flop circuit is implemented in a first NWell that electrically contacts the deep isolation NWell, the first NWell is connected to a first bias voltage that is less than a positive power supply voltage, and the first PWell is connected to a second bias voltage that is greater than a negative power supply voltage.


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