The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Nov. 27, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Chin-Shan Wang, Hsinchu, TW;

Yi-Miaw Lin, Taipei County, TW;

Ming-Yih Wang, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 29/49 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); H01L 29/41791 (2013.01); H01L 29/42372 (2013.01); H01L 29/49 (2013.01); H01L 29/66795 (2013.01);
Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductive substrate, and a first contact plug formed on the semiconductive substrate. The semiconductor structure further includes a dielectric layer encircling the first contact plug. The semiconductor structure further includes a multilayer structure deposited on the dielectric layer and encircling the first contact plug. The dielectric layer produces a tensile stress pulling the first contact plug outward along a width direction. The multilayer structure produces a compressive stress that compensates for the tensile stress caused by the dielectric layer. A method of forming the semiconductor structure is also provided.


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