The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Aug. 21, 2017
Applicant:

Csmc Technologies Fab2 Co., Ltd., Jiangsu, CN;

Inventors:

Yan Gu, Jiangsu, CN;

Shikang Cheng, Jiangsu, CN;

Sen Zhang, Jiangsu, CN;

Assignee:

CSMC TECHNOLOGIES FAB2 CO., LTD., Wuxi New District, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/808 (2006.01); H01L 21/337 (2006.01); H01L 27/07 (2006.01); H01L 29/10 (2006.01); H01L 21/265 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0705 (2013.01); H01L 21/265 (2013.01); H01L 21/823412 (2013.01); H01L 21/823425 (2013.01); H01L 21/823487 (2013.01); H01L 21/823493 (2013.01); H01L 29/10 (2013.01); H01L 29/66 (2013.01); H01L 29/808 (2013.01);
Abstract

A device integrated with a depletion-mode junction field-effect transistor and a method for manufacturing the device. The device includes: a well region, which is of a second conduction type and formed within a first conduction region (); a JFET source (), which is of a first conduction type and formed within the well region; a metal electrode () of the JFET sources formed on the JFET sources (), which is in contact with the JFET sources (); a lateral channel region (), which is of the first conduction type and formed between two adjacent JFET sources (), while two ends thereof are in contact with the two adjacent JFET sources (); and a JFET metal gate () formed on the well region.


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