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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10867921 B1

PDFFull Text
Date of Patent:
Dec. 15, 2020

Filed:

May. 24, 2019

Semiconductor structure with tapered conductor

Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Wei Ting Chen, Hsinchu, TW;

Che-Cheng Chang, New Taipei, TW;

Chen-Hsiang Lu, Hsin-Chu, TW;

Yu-Cheng Liu, Hsinchu County, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu, TW;

Attorneys:

WPAT, P.C., Intellectual Property Attorneys

Anthony King

Primary Examiner:

Caleb E Henry

Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/532 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 21/027 (2006.01); H01L 21/288 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53238 (2013.01); H01L 21/0276 (2013.01); H01L 21/2885 (2013.01); H01L 21/3212 (2013.01); H01L 21/7684 (2013.01); H01L 21/76804 (2013.01); H01L 21/76811 (2013.01); H01L 21/76816 (2013.01); H01L 21/76834 (2013.01); H01L 21/76846 (2013.01); H01L 21/76874 (2013.01); H01L 21/76879 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 23/53295 (2013.01);
Abstract

A semiconductor structure includes an etching stop layer over an inter-layer dielectric (ILD) layer; a low-k dielectric layer over the etching stop layer; and a tapered conductor extending through the low-k dielectric layer and the etching stop layer and partially through the ILD layer; wherein the tapered conductor includes a recess disposed within the ILD layer and indented towards the etching stop layer and the low-k dielectric layer, and a protrusion surrounding the recess and protruded from the etching stop layer towards the ILD layer.

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