The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Jan. 15, 2019
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Jaladhi Mehta, Clifton Park, NY (US);

Brian Greene, Portland, OR (US);

Daniel J. Dechene, Watervliet, NY (US);

Ahmed Hassan, Clifton Park, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 23/522 (2006.01); H01L 49/02 (2006.01); H01L 21/76 (2006.01); H01L 29/78 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5228 (2013.01); H01L 21/76 (2013.01); H01L 28/20 (2013.01); H01L 21/823821 (2013.01); H01L 23/5223 (2013.01); H01L 29/785 (2013.01);
Abstract

Structures that include a passive device, such as a metal-based resistor, and methods of forming a structure that includes a passive device. The structure includes a semiconductor substrate, an interconnect structure including a passive device, and a dummy fill region arranged between the passive device and the semiconductor substrate. The dummy fill region includes a plurality of shallow trench isolation regions in the semiconductor substrate, a plurality of semiconductor fins, a plurality of source/drain regions in the plurality of semiconductor fins, and a plurality of contacts arranged over the plurality of shallow trench isolation regions.


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