The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Nov. 09, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Chih-Kuang Kao, Hsin-Chu County, TW;

Ta-Chih Peng, Hsinchu, TW;

Ming-Hong Kao, Hsinchu, TW;

Huei-Wen Yang, Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 23/522 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 49/02 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 21/0254 (2013.01); H01L 21/02532 (2013.01); H01L 21/02554 (2013.01); H01L 24/17 (2013.01); H01L 25/0657 (2013.01); H01L 28/60 (2013.01);
Abstract

The present disclosure provides a semiconductor package, including at least two conductors and a first dielectric partially surrounding the at least two conductors, a capacitor substantially under the first dielectric, and a second dielectric over and lining along the first dielectric and top portions of the at least two conductors. The at least two conductors are respectively configured as an input/output (I/O) terminal of the semiconductor package. The capacitor includes a first electrode extending along a first direction and electrically connected with one of the at least two conductors, and a second electrode extending along a second direction opposite to the first direction and electrically connected to the other one of the at least two conductors. The second dielectric provides a compressive stress to the first dielectric. A method of forming the semiconductor package is also provided.


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