The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Jan. 04, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Michael Clinton, Austin, TX (US);

Bryan David Sheffield, Austin, TX (US);

Marty Tsai, Hsinchu, TW;

Rajinder Singh, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/24 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 7/18 (2006.01); G11C 11/417 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 16/24 (2013.01); G11C 7/106 (2013.01); G11C 7/1039 (2013.01); G11C 7/12 (2013.01); G11C 7/18 (2013.01); G11C 11/417 (2013.01); G11C 11/419 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01);
Abstract

A memory device includes an array of memory cells that has a first sub array and a second sub array. A plurality of bit lines are connected to the memory cells, and an IO block is situated between the first sub array and the second sub array. The bit lines extend from the first and second memory sub arrays of the memory device directly to the IO block. The IO block further includes data input and output terminals configured to receive data to be written to the array of memory cells and output data read from the array of memory cells via the plurality of bit lines.


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