The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

May. 02, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shang-Chih Hsieh, Yangmei, TW;

Hui-Zhong Zhuang, Kaohsiung, TW;

Ting-Wei Chiang, New Taipei, TW;

Chun-Fu Chen, Chiayi, TW;

Hsiang-Jen Tseng, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); H01L 21/768 (2006.01); H01L 27/118 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); H01L 21/768 (2013.01); H01L 27/0207 (2013.01); H01L 27/11807 (2013.01); H01L 2027/11875 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An integrated circuit designing system includes a non-transitory storage medium, the non-transitory storage medium being encoded with a layout of a standard cell corresponding to a predetermined manufacturing process, the predetermined manufacturing process having a nominal minimum pitch of metal lines along a predetermined direction, the layout of the standard cell having a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The integrated circuit designing system further includes a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.


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