The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Jun. 26, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Prashant Dewan, Hillsboro, OR (US);

Uttam K. Sengupta, Portland, OR (US);

Siddhartha Chhabra, Portland, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G06F 12/1027 (2016.01); G06F 12/1009 (2016.01); G06F 12/109 (2016.01); G06F 12/10 (2016.01); G06F 12/1036 (2016.01);
U.S. Cl.
CPC ...
G06F 12/145 (2013.01); G06F 12/10 (2013.01); G06F 12/1009 (2013.01); G06F 12/109 (2013.01); G06F 12/1027 (2013.01); G06F 12/14 (2013.01); G06F 12/1036 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/651 (2013.01); G06F 2212/657 (2013.01); G06F 2212/68 (2013.01);
Abstract

Technologies for protecting virtual machine memory of a compute device include a virtual machine (VM) instantiated on the compute device, a virtual machine monitor (VMM) established on the compute device to control operation of the VM, a secured memory, and a memory manager. The memory manager receives a memory access request that includes a virtual linear address (LA) from the VM and performs a translation of the LA to a translated host physical address (HPA) of the compute device using one or more page tables associated with the VM and VMM. The memory manager determines whether a secured translation mapping of LA-to-HPA that corresponds to the LA is locked. If the mapping is locked, the memory manager verifies the translation based on a comparison of the translated HPA to a HPA translated using the secured translation mapping and, if verified, performs the memory access request using the translated HPA.


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