The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Mar. 28, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventor:

Philippe Molson, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/00 (2006.01); G01R 31/317 (2006.01); G01R 31/3177 (2006.01); G06F 21/57 (2013.01); G06F 9/4401 (2018.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31704 (2013.01); G01R 31/3177 (2013.01); G01R 31/31705 (2013.01); G06F 9/4401 (2013.01); G06F 13/4282 (2013.01); G06F 13/4295 (2013.01); G06F 21/575 (2013.01); G06F 2213/0026 (2013.01); G06F 2221/034 (2013.01);
Abstract

A test system is provided for performing design for debug (DFD) operations. The test system includes a host processor coupled to an auxiliary device. The auxiliary device includes a protocol interface block for communicating with the host processor during normal functional mode. The auxiliary device further includes a circuit under test (CUT) and a hardened DFD hub that is controlled by the host processor via the protocol interface block. The DFD hub includes a DFD triggering component, a DFD tracing component, and a DFD access component. The host processor directs the DFD hub to perform DFD operations by sending control signals through the protocol interface block during a debugging mode. Test information gathered using the DFD hub is fed back to the host processor to help facilitate silicon bring-up, pre-production software stack optimization, and post-production performance metric monitoring.


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