The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2020
Filed:
Mar. 06, 2019
Applicant:
At&s Austria Technologie & Systemtechnik Aktiengesellschaft, Leoben, AT;
Inventors:
Johannes Stahr, St. Lorenzen im Mürztal, AT;
Timo Schwarz, St. Michael i.O., AT;
Mario Schober, Trofaiach, AT;
Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H05K 3/00 (2006.01); H05K 3/46 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 23/00 (2006.01); H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 3/40 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4602 (2013.01); H01L 21/56 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/5329 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 24/19 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H05K 1/0298 (2013.01); H05K 1/112 (2013.01); H05K 1/181 (2013.01); H05K 1/185 (2013.01); H05K 3/4038 (2013.01); H05K 3/4682 (2013.01); H01L 2223/54493 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/12105 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/14 (2013.01); H01L 2924/18162 (2013.01); H01L 2924/3511 (2013.01); H01L 2924/35121 (2013.01); H05K 3/0052 (2013.01); H05K 3/0097 (2013.01); H05K 2201/0154 (2013.01); H05K 2201/10378 (2013.01); H05K 2203/025 (2013.01); H05K 2203/166 (2013.01);
Abstract
A manufacturing method, wherein the method includes providing a layer stack having at least partially uncured component carrier material, arranging a plurality of components in recesses of the layer stack, integrally connecting the components with the layer stack by curing the component carrier material, and applying a high temperature robust dielectric structure on a main surface of the cured layer stack with the components therein.