Arbitrary rate decimator and timing error corrector for an fsk receiver

Abstract

An arbitrary rate digital decimator filter () and associated method are disclosed for filtering a digital data stream with a plurality of cascaded power-of-two decimator stages () connected to receive the digital data stream and to generate a first filtered digital signal which is provided to a fractional resampling stage () which generates a second filtered digital signal with delta-sigma modulator () and a limited integrator stage () connected to receive a first control () word and a feedback clock signal () with inserted or swallowed pulses which is generated by a clock generator in response to pulse commands generated by the limited integrator stage, wherein the limited integrator is configured to generate time shift commands () to a timing shift filter () which performs fractional interpolation on the first filtered digital signal to generate the second filtered digital signal.