The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2020

Filed:

Sep. 23, 2019
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Benjamin Colombeau, Salem, MA (US);

Sheng-Chin Kung, Milpitas, CA (US);

Patricia M. Liu, Saratoga, CA (US);

Assignee:

APPLIED MATERIALS, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); H01L 21/3065 (2006.01); H01L 21/02 (2006.01); H01L 29/165 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67167 (2013.01); H01L 21/02057 (2013.01); H01L 21/02532 (2013.01); H01L 21/3065 (2013.01); H01L 21/67028 (2013.01); H01L 21/67069 (2013.01); H01L 21/67196 (2013.01); H01L 21/67201 (2013.01); H01L 21/67207 (2013.01); H01L 29/165 (2013.01); H01L 29/401 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01);
Abstract

Generally, examples described herein relate to integrated solutions for forming cladding layers on trimmed layers that were formed as part of a superlattice. In an example, a first material is selectively etched in a first processing chamber of a processing system. The first material is disposed within alternating layers of the first material and a second material in a channel region on a substrate. A portion of the second material is trimmed in the first processing chamber of the processing system. The substrate is transferred from the first processing chamber of the processing system to a second processing chamber of the processing system without exposing the substrate to an ambient environment exterior to the processing system. A cladding layer is epitaxially grown on respective layers of the trimmed second material in the second processing chamber of the processing system.


Find Patent Forward Citations

Colombeau, Benjamin. (2020). Integrated semiconductor processing (U.S. Patent No. 10861722). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10861722

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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