The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2020

Filed:

Mar. 26, 2020
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Yusuke Higashi, Zushi, JP;

Yuuichi Kamimuta, Yokkaichi, JP;

Tsunehiro Ino, Fujisawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); H01L 29/51 (2006.01); H01L 27/1159 (2017.01); H01L 29/78 (2006.01); H01L 27/11507 (2017.01); H01L 49/02 (2006.01); H01L 27/11597 (2017.01); H01L 29/06 (2006.01); H01L 29/775 (2006.01);
U.S. Cl.
CPC ...
G11C 11/225 (2013.01); G11C 11/221 (2013.01); G11C 11/223 (2013.01); G11C 11/2275 (2013.01); H01L 27/1159 (2013.01); H01L 27/11507 (2013.01); H01L 27/11597 (2013.01); H01L 28/40 (2013.01); H01L 29/516 (2013.01); H01L 29/78391 (2014.09); H01L 29/0676 (2013.01); H01L 29/775 (2013.01);
Abstract

A semiconductor memory device according to one embodiment includes: a memory cell, the memory cell including a ferroelectric film; and a control circuit controlling the memory cell. Additionally, the control circuit determining whether the number of times of executions of a write process or an erase process on the memory cell has reached a predetermined number of times; and, if the number of times of executions has reached the predetermined number of times, executing a voltage application process in which a first voltage of a first polarity and a second voltage of a second polarity opposite to the first polarity are applied to the ferroelectric film.


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