The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2020
Filed:
Aug. 10, 2018
Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;
Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;
Duohui Bei, Shanghai, CN;
Abstract
The present disclosure provides methods and apparatus for designing an interconnection structure and methods for manufacturing an interconnection structure, and relates to the technical field of semiconductors. An implementation of the method may include: designing n virtual interconnection units according to a number of metal interconnection layers in a circuit area of a chip design drawing, where an ivirtual interconnection unit includes i metal interconnection layers, and where adjacent metal interconnection layers in a jvirtual interconnection unit are connected by using vias, and n≥2, 1≤i≤n, and 2≤j≤n; and filling an area in the chip design drawing outside the circuit area with virtual interconnection units, where the jvirtual interconnection unit is filled, and a (j−1)virtual interconnection unit is not filled unless there is no space in the area for the jvirtual interconnection unit.