The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2020
Filed:
Sep. 24, 2015
Cadence Design Systems, Inc., San Jose, CA (US);
Mitchell G. Poplack, San Jose, CA (US);
Yuhei Hayashi, San Jose, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Disclosed herein are systems and methods of compiling resources of a programmable emulation system to execute an emulation process, to emulate a logic system, such as an application-specific integrated circuit (ASIC), currently being tested and prototyped, and then revising, transforming, and moving the compiled instructions sets to inexpensively, quickly, and dynamically adapt to unavailable resources, which may be due to previously allocation to a different emulation job, or for fault tolerance. Relocation of the resources that will execute the emulation job (i.e., 'footprint') may refer to the remapping of a compiled footprint to a revised set of resources, defining a revised footprint. Fault tolerance may refer to support for working around faulty hardware components of the emulation system.