The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2020
Filed:
Jun. 04, 2019
Ansys, Inc., Canonsburg, PA (US);
Renuka Vanukuri, Cupertino, CA (US);
Seema Naswa, Noida, IN;
Ansys, Inc., Canonsburg, PA (US);
Abstract
Example systems and methods are disclosed for estimating power consumption by a clock tree in a register-transfer level (RTL) circuit design based on a previously generated reference gate-level circuit design. A plurality of regions within the clock tree structure of the reference gate-level circuit design are identified, where the plurality of regions are demarcated by one or more clock gating structures. A region-based clock model is generated that includes at least one clock constraint model for each identified region. The region-based clock model is used to synthesize the clock tree in the RTL circuit design for estimating power consumption.