The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2020

Filed:

Jun. 21, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Swadesh Choudhary, Mountain View, CA (US);

Bahaa Fahim, Santa Clara, CA (US);

Mahesh Wagh, Portland, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 13/40 (2006.01); G06F 11/07 (2006.01); G06F 13/42 (2006.01); G06F 11/10 (2006.01); G06F 11/18 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4068 (2013.01); G06F 11/0745 (2013.01); G06F 11/0751 (2013.01); G06F 11/0772 (2013.01); G06F 11/1004 (2013.01); G06F 11/18 (2013.01); G06F 13/42 (2013.01);
Abstract

Herein is disclosed an integrated input/output ('I/O') processing system, comprising an I/O port, configured to receive I/O data and to deliver the I/O data to one or more processors; one or more processors, further comprising a first processing logic and a second processing logic, wherein the one or more processors are configured to deliver the received I/O data to the first processing logic and to the second processing logic, and wherein the first processing logic and the second processing logic are configured to redundantly process the I/O data; and a comparator, configured to compare an output of the first processing logic and an output of the second processing logic.


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