The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2020

Filed:

Mar. 30, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mark Dechene, Hillsboro, OR (US);

Manjunath Shevgoor, San Jose, CA (US);

Faruk Guvenilir, Austin, TX (US);

Zhongying Zhang, Portland, OR (US);

Jonathan Perry, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/32 (2018.01); G06F 12/1027 (2016.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30043 (2013.01); G06F 9/30036 (2013.01); G06F 9/322 (2013.01); G06F 9/3818 (2013.01); G06F 12/1027 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/657 (2013.01);
Abstract

An apparatus and method for early page address prediction. For example, one embodiment of a processor comprises: an instruction fetch circuit to fetch a load instruction; a decoder to decode the load instruction; execution circuitry to execute the load instruction to perform a load operation, the execution circuitry including an address generation unit (AGU) to generate an effective address to be used for the load operation; and early page prediction (EPP) circuitry to use one or more attributes associated with the load instruction to predict a physical page address for the load instruction simultaneously with the AGU generating the effective address and/or prior to generation of the effective address.


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