The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2020
Filed:
Nov. 13, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Prashant Majhi, San Jose, CA (US);
Khaled Hasnat, San Jose, CA (US);
Krishna Parat, Palo Alto, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 29/78 (2006.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 29/04 (2006.01); H01L 27/11582 (2017.01); H01L 29/16 (2006.01); H01L 27/1157 (2017.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7843 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 29/04 (2013.01); H01L 29/16 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08);
Abstract
A memory structure can include a conductive channel, a charge storage structure adjacent to the conductive channel, and a strain-inducing layer adjacent to the conductive channel on a side opposite the charge storage structure. The strain-inducing layer can have a higher coefficient of thermal expansion (CTE) than the conductive channel.