The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2020
Filed:
Sep. 20, 2019
Justin Andrew Parke, Ellicott City, MD (US);
Eric J. Stewart, Silver Spring, MD (US);
Robert S. Howell, Silver Spring, MD (US);
Howell George Henry, Ellicott City, MD (US);
Bettina Nechay, Laurel, MD (US);
Harlan Carl Cramer, Columbia, MD (US);
Matthew Russell King, Linthicum, MD (US);
Shalini Gupta, Baltimore, MD (US);
Ronald G. Freitag, Catonsville, MD (US);
Karen Marie Renaldo, Pasadena, CA (US);
Justin Andrew Parke, Ellicott City, MD (US);
Eric J. Stewart, Silver Spring, MD (US);
Robert S. Howell, Silver Spring, MD (US);
Howell George Henry, Ellicott City, MD (US);
Bettina Nechay, Laurel, MD (US);
Harlan Carl Cramer, Columbia, MD (US);
Matthew Russell King, Linthicum, MD (US);
Shalini Gupta, Baltimore, MD (US);
Ronald G. Freitag, Catonsville, MD (US);
Karen Marie Renaldo, Pasadena, CA (US);
NORTHROP GRUMMAN SYSTEMS CORPORATION, Falls Church, VA (US);
Abstract
A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact.