The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2020

Filed:

Nov. 30, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Cheng-I Huang, Hsinchu, TW;

Ting-Wei Chiang, New Taipei, TW;

Shih-Chi Fu, Hsinchu County, TW;

Sheng-Fang Cheng, New Taipei, TW;

Jung-Chan Yang, Taoyuan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); G06F 30/39 (2020.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); G06F 30/39 (2020.01); H01L 27/0886 (2013.01); H01L 29/66545 (2013.01); H01L 21/823431 (2013.01);
Abstract

A method includes the operations below. A first and second layout patterns corresponding to a first and second area are placed. Third layout patterns corresponding to a first continuous fin over the first area and second area, and corresponding to a second fin including separate portions spaced apart by a first recess over the first area are placed. A fourth layout pattern, corresponding to a dummy gate, at the recess portion and between the first layout pattern and the second layout pattern, is placed to generate a layout design of a semiconductor device. A side of the second area facing the first recess is substantially flat, and the semiconductor device is fabricated by a tool based on the layout design. A first length of the first continuous fin is equal to a sum of a second length of the second fin and a third length of the first recess.


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