The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2020

Filed:

May. 20, 2019
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chia-Lin Lu, Taoyuan, TW;

Chun-Lung Chen, Tainan, TW;

Kun-Yuan Liao, Hsinchu, TW;

Chun-Hsien Lin, Tainan, TW;

Wei-Hao Huang, New Taipei, TW;

Kai-Teng Cheng, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/321 (2006.01); H01L 21/28 (2006.01); H01L 21/30 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82345 (2013.01); H01L 21/28088 (2013.01); H01L 21/3003 (2013.01); H01L 21/3212 (2013.01); H01L 21/823462 (2013.01); H01L 21/823842 (2013.01); H01L 27/092 (2013.01);
Abstract

The present invention provides a method for forming a semiconductor structure. The method including: Firstly, a substrate is provided, a first region and a second region are defined thereon, next, a gate dielectric layer and a work function metal layer are sequentially formed on the substrate within the first region and within the second region. Afterwards, a dielectric layer is formed on the work function metal layer within the second region, a hydrogen gas treatment is then performed on the substrate, and the work function metal layer is removed within the first region.


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