The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2020

Filed:

Jan. 10, 2020
Applicant:

Yield Microelectronics Corp., Chu-Pei, TW;

Inventors:

Cheng-Ying Wu, Chu-Pei, TW;

Cheng-Yu Chung, Chu-Pei, TW;

Wen-Chien Huang, Chu-Pei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/04 (2006.01); H01L 27/11521 (2017.01); G11C 16/08 (2006.01); G11C 16/14 (2006.01); G11C 16/24 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/14 (2013.01); G11C 16/24 (2013.01); H01L 27/11521 (2013.01);
Abstract

An operating method of low current electrically erasable programmable read only memory (EEPROM) array is provided. The EEPROM array comprises a plurality of bit line groups, word lines, common source lines, and sub-memory arrays. A first memory cell of each sub-memory array is connected with one bit line of a first bit line group, a first common source line, and a first word line. A second memory cell of each sub-memory array is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are symmetrically arranged at two opposite sides of the first common source line. By employing the proposed specific operation and bias conditions of the present invention, rapidly bytes programming and erasing functions with low current, low voltage and low cost goals are accomplished.


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