The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2020

Filed:

Jul. 17, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Setul M. Shah, Folsom, CA (US);

William Sheung, Folsom, CA (US);

Dhruval J. Patel, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G11C 16/10 (2006.01); H02M 3/07 (2006.01); G05F 1/575 (2006.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
G11C 5/147 (2013.01); G05F 1/575 (2013.01); G11C 16/10 (2013.01); G11C 16/30 (2013.01); H02M 3/07 (2013.01);
Abstract

Techniques to adapt the DC bias of voltage regulators for memory devices as a function of bandwidth demand are described. In one example, a non-volatile memory device includes a plurality of voltage regulator slices, wherein outputs of the plurality of voltage regulators slices are tied together to provide a voltage to perform operations on the array. The voltage regulator slices can be enabled or disabled based on a signal from a memory controller, such as an indication of an upcoming change in bandwidth demand for a rank including the memory device.


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