The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2020
Filed:
Mar. 13, 2017
Applicant:
Synopsys, Inc., Mountain View, CA (US);
Inventors:
Ramesh Narayanaswamy, Palo Alto, CA (US);
Paraminder S. Sahai, San Jose, CA (US);
Chiahon Chien, Saratoga, CA (US);
Assignee:
SYNOPSYS, INC., Mountain View, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/20 (2020.01); G06F 30/3323 (2020.01); G06F 30/367 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3323 (2020.01); G06F 30/20 (2020.01); G06F 30/367 (2020.01);
Abstract
Computer implemented techniques for the partitioned simulation of parallel architectures are disclosed. A high-level design for simulation is obtained. A graph representation for the high-level design is determined. The graph for the high-level design is partitioned into sub-graphs. A subset of the sub-graphs is selected for simulation based on input-change bits of the sub-graphs. The subset of the sub-graphs is subsequently evaluated on parallel architectures in order to produce a simulation result for the high-level design.