The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2020
Filed:
Jun. 14, 2019
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Samit Sengupta, San Diego, CA (US);
Anil Chowdary Kota, San Diego, CA (US);
Fadoua Chafik, San Diego, CA (US);
Assignee:
QUALCOMM Incorporated—, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G01R 31/00 (2006.01); G06F 30/327 (2020.01); G06F 30/33 (2020.01); G06F 30/34 (2020.01); G06F 30/3323 (2020.01); G01R 31/3183 (2006.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/33 (2020.01); G06F 30/3323 (2020.01); G06F 30/34 (2020.01); G01R 31/318371 (2013.01);
Abstract
A method for repairing logic design includes inserting primary logic gates in a primary logic design path of a logic chip. The method also includes inserting alternative logic gates in an alternate logic design path of the logic chip. The alternate logic design path and the primary logic design path are coupled to multiple fuses. The potentially defective design is repaired by selecting between the alternate logic design path and the primary logic design path with the fuses when the logic design is defective.