The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2020

Filed:

Jun. 24, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Cunming Liang, Shanghai, CN;

Danny Y. Zhou, Shanghai, CN;

David E. Cohen, Hull, MA (US);

James R. Harris, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 3/00 (2006.01); G06F 9/50 (2006.01); G06F 13/28 (2006.01); G06F 13/42 (2006.01); G06F 9/455 (2018.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); G06F 3/00 (2013.01); G06F 9/5077 (2013.01); G06F 13/28 (2013.01); G06F 13/4282 (2013.01); G06F 9/5011 (2013.01); G06F 2009/45579 (2013.01); G06F 2213/0026 (2013.01);
Abstract

Disclosed herein are systems and methods for isolating input/output computing resources. In some embodiments, a host device may include logic to identify a Process Address Space Identifier (PASID) for a process or container of the host device and logic to associate the PASID with an individual queue pair of a hardware device of the host device, wherein the queue pair includes two complementary queues and wherein the queue pair is owned by the process or container upon association with the PASID. Other embodiments may be disclosed and/or claimed.


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