The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2020

Filed:

Jun. 28, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Yikui Dong, Cupertino, CA (US);

Shenggao Li, Cupertino, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 7/30 (2006.01); H03H 7/40 (2006.01); H03K 5/159 (2006.01); H04L 25/03 (2006.01); H04L 25/49 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03267 (2013.01); H04L 25/03025 (2013.01); H04L 25/4902 (2013.01);
Abstract

Embodiments include apparatuses, methods, and systems including a decision feedback equalizer (DFE). The DFE includes a first summer circuit, a second summer circuit, a decision circuit, and a tap-delay line including a number of delay elements. The first summer circuit is to add together an analog signal and a first set of weighted feedback taps {h(j+1), . . . h(m)} of time delayed signals of a detected symbol to generate a first summand. The second summer circuit is to add together a second set of weighted feedback taps {h(k+1), h(n)} of time delayed signals of the detected symbol to generate a second summand. The decision circuit is to receive at least the first summand and the second summand, to generate the detected symbol based on a sum including the first summand and the second summand. Other embodiments may also be described and claimed.


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