The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2020

Filed:

Jul. 20, 2020
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Dinesh Joshi, Delhi, IN;

Nidhi Sinha, Noida, IN;

Akshay Kumar Pathak, Noida, IN;

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/19 (2006.01); H03K 5/1534 (2006.01); H03K 5/00 (2006.01); G06F 1/04 (2006.01); H03K 5/26 (2006.01);
U.S. Cl.
CPC ...
H03K 5/19 (2013.01); H03K 5/1534 (2013.01); G06F 1/04 (2013.01); H03K 5/26 (2013.01); H03K 2005/00013 (2013.01);
Abstract

System and method for detecting clock failure are disclosed. The system includes a pulse train generator, a delay circuit, and a failure detection circuit. The pulse train generator receives an input clock and generates a pulse train including a plurality of pulses aligned with a set of rising edges and a set of falling edges of the input clock. The delay circuit delays the input clock by a first time-interval to generate a first delayed clock. The failure detection circuit receives the pulse train and the first delayed clock from the pulse train generator and the delay circuit, respectively, and generates a clock detection signal that transitions from a first logic state to a second logic state based on a failure in the input clock.


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