The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2020

Filed:

Jul. 24, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kurt D. Beigel, Boise, ID (US);

Scott E. Sills, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 21/822 (2006.01); H01L 21/8238 (2006.01); G11C 29/44 (2006.01); G11C 5/02 (2006.01); G11C 29/14 (2006.01); G11C 29/12 (2006.01); G11C 7/10 (2006.01); H01L 29/66 (2006.01); H01L 27/105 (2006.01); G11C 29/00 (2006.01); G11C 29/42 (2006.01); G11C 7/12 (2006.01); G11C 5/14 (2006.01); H03K 19/20 (2006.01); H03K 19/0948 (2006.01); G11C 8/10 (2006.01); G11C 8/08 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0688 (2013.01); G11C 5/025 (2013.01); G11C 7/10 (2013.01); G11C 29/1201 (2013.01); G11C 29/14 (2013.01); G11C 29/42 (2013.01); G11C 29/44 (2013.01); G11C 29/4401 (2013.01); G11C 29/72 (2013.01); G11C 29/81 (2013.01); H01L 21/8221 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823885 (2013.01); H01L 27/092 (2013.01); H01L 27/1052 (2013.01); H01L 29/0642 (2013.01); H01L 29/42392 (2013.01); H01L 29/6675 (2013.01); H01L 29/78642 (2013.01); H01L 29/78696 (2013.01); G11C 5/145 (2013.01); G11C 5/147 (2013.01); G11C 7/12 (2013.01); G11C 8/08 (2013.01); G11C 8/10 (2013.01); H03K 19/0948 (2013.01); H03K 19/20 (2013.01);
Abstract

A semiconductor device includes a stack structure comprising decks. Each deck of the stack structure comprises a memory element level comprising memory elements and control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region or the N-type channel region overlying the first subdeck structure. Related semiconductor devices and methods of forming the semiconductor devices are disclosed.


Find Patent Forward Citations

Loading…