The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2020

Filed:

Mar. 14, 2018
Applicant:

Raytheon Company, Waltham, MA (US);

Inventors:

Scott S. Miller, Waltham, MA (US);

Christine Frandsen, Waltham, MA (US);

Andrew Cahill, Waltham, MA (US);

Sean P. Kilcoyne, Waltham, MA (US);

Shannon Wilkey, Waltham, MA (US);

Assignee:

Raytheon Company, Waltham, MA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 22/20 (2013.01); H01L 23/562 (2013.01); H01L 21/6835 (2013.01); H01L 22/12 (2013.01);
Abstract

Disclosed is a process for manufacturing individual die devices, with a desired or predicted amount of flatness, from a bonded wafer process. The flatness of a bonded wafer is measured at point in the wafer manufacturing process. This measurement is compared to a value predetermined by an empirical analysis of previous devices made by the same process. If the flatness of the bonded wafer is not at the predetermined value, then one or more compensation layers are provided to the bonded wafer to obtain the predetermined flatness value. Once obtained, subsequent processing is performed and the resulting individual dies are obtained with the desired flatness characteristic.


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