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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10847409 B1

PDFFull Text
Date of Patent:
Nov. 24, 2020

Filed:

Nov. 01, 2018

Semiconductor device and method

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Shiang-Bau Wang, Pingzchen, TW;

Chun-Hung Lee, Hsinchu, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Marcos D Pizarro

Assistant Examiner:

Sue Tang

Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 21/3105 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76229 (2013.01); H01L 21/31053 (2013.01); H01L 21/76232 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02282 (2013.01); H01L 21/02337 (2013.01); H01L 21/02356 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01);
Abstract

A method for shallow trench isolation structures in a semiconductor device and a semiconductor device including the shallow trench isolation structures are disclosed. In an embodiment, the method may include forming a trench in a substrate; depositing a first dielectric liner in the trench; depositing a first shallow trench isolation (STI) material over the first dielectric liner, the first STI material being deposited as a conformal layer; etching the first STI material; depositing a second STI material over the first STI material, the second STI material being deposited as a flowable material; and planarizing the second STI material such that top surfaces of the second STI material are co-planar with top surfaces of the substrate.

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