The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2020

Filed:

Jan. 11, 2017
Applicant:

Illumina, Inc., San Diego, CA (US);

Inventors:

Pieter van Rooyen, La Jolla, CA (US);

Robert J. McMillen, La Jolla, CA (US);

Michael Ruehle, La Jolla, CA (US);

Rami Mehio, La Jolla, CA (US);

Assignee:

Illumina, Inc., San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G16B 30/00 (2019.01); H01L 27/118 (2006.01); H01L 27/02 (2006.01); H01L 49/02 (2006.01); H03K 19/17736 (2020.01); G16B 50/00 (2019.01);
U.S. Cl.
CPC ...
G16B 30/00 (2019.02); G16B 50/00 (2019.02); H01L 27/0207 (2013.01); H01L 27/118 (2013.01); H01L 27/11807 (2013.01); H01L 28/00 (2013.01); H03K 19/17736 (2013.01); H01L 2027/11838 (2013.01); H01L 2027/11883 (2013.01);
Abstract

A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes a integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.


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