The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2020

Filed:

Jun. 28, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Anatoli Bolotov, San Jose, CA (US);

Mikhail Grinchuk, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/64 (2013.01); G06F 11/10 (2006.01); G06F 12/0815 (2016.01); H04L 9/08 (2006.01); G06F 21/79 (2013.01); G11C 29/52 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 21/64 (2013.01); G06F 11/1048 (2013.01); G06F 11/1068 (2013.01); G06F 12/0815 (2013.01); G06F 21/79 (2013.01); H04L 9/0891 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/402 (2013.01); G11C 29/52 (2013.01); G11C 2029/0411 (2013.01);
Abstract

System and techniques for compressed integrity check counters in memory are described herein. A set of counters may be maintained for data areas in memory. A respective counter is the set of counters is used to provide a variance to encryption operations on a corresponding data area. The respective counter is each time data is modified in the corresponding data area. The respective counter implemented by a generalized multi-dimensional counter (GMDC). In response to a trigger, a counter reset is performed on the set of counters. The counter reset may include refreshing the corresponding data area using a new key and resetting the respective counter to a default value in response to the refresh.


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