The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2020

Filed:

Mar. 14, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Nusrat Islam, Bee Cave, TX (US);

Gengbin Zheng, Austin, TX (US);

Sayantan Sur, Portland, OR (US);

Maria Garzaran, Champaign, IL (US);

Akhil Langer, Champaign, IL (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 16/90 (2019.01); G06F 13/00 (2006.01); G06F 8/00 (2018.01); G06F 13/16 (2006.01); G06F 16/901 (2019.01);
U.S. Cl.
CPC ...
G06F 13/16 (2013.01); G06F 8/00 (2013.01); G06F 16/9024 (2019.01); G06F 2213/16 (2013.01);
Abstract

Examples include a computing system having an input/output (I/O) device including a plurality of counters, each counter operating as one of a completion counter and a trigger counter, a processing device; and a memory device. The memory device stores instructions that, in response to execution by the processing device, cause the processing device to represent a plurality of triggered operations of collective communication for high-performance computing executable by the I/O device as a directed acyclic graph stored in the memory device, with triggered operations represented as vertices of the directed acyclic graph and dependencies between triggered operations represented as edges of the directed acyclic graph; traverse the directed acyclic graph using a first process to identify and mark vertices that can share a completion counter; and traverse the directed acyclic graph using a second process to assign a completion counter and a trigger counter for each vertex.


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