Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices

Abstract

Semiconductor memory device includes a memory cell array and an interface circuit including an ECC engine. The memory cell array includes a normal cell region and a parity cell region including a first sub parity region and a second sub parity region. The interface circuit receives main data and sub data comprising external parity or a data mask signal, generates a flag signal based on mask bits of the data mask signal, performs ECC encoding operation on the main data in response to an operation mode and the flag signal, stores the main data in the normal cell region, stores either the external parity or the flag signal in the second sub parity region in response to the operation mode, performs an ECC decoding operation on the main data read from the normal cell region in response to the operation mode and the flag signal.