The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 2020
Filed:
Jun. 30, 2017
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Yipeng Wang, Hillsboro, OR (US);
Ren Wang, Portland, OR (US);
Sameh Gobriel, Hillsboro, OR (US);
Tsung-Yuan Charlie Tai, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/128 (2016.01); H04L 12/747 (2013.01); G06F 12/0875 (2016.01); G06F 12/0813 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0611 (2013.01); G06F 3/067 (2013.01); G06F 3/0607 (2013.01); G06F 3/0613 (2013.01); G06F 3/0635 (2013.01); G06F 12/0875 (2013.01); G06F 12/128 (2013.01); H04L 45/742 (2013.01); G06F 12/0813 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/154 (2013.01); G06F 2212/502 (2013.01);
Abstract
Examples may include techniques to control an insertion ratio or rate for a cache. Examples include comparing cache miss ratios for different time intervals or windows for a cache to determine whether to adjust a cache insertion ratio that is based on a ratio of cache misses to cache insertions.