The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 2020
Filed:
Jun. 24, 2019
Intel Corporation, Santa Clara, CA (US);
Xiaosen Liu, Portland, OR (US);
Harish Krishnamurthy, Beaverton, OR (US);
Krishnan Ravichandran, Saratoga, CA (US);
Vivek De, Beaverton, OR (US);
Scott Chiu, Folsom, CA (US);
Claudia Patricia Barrera Gonzalez, Campbell, CA (US);
Jing Han, Mountain View, CA (US);
Rajasekhara Madhusudan Narayana Bhatla, Santa Clara, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments of the present disclosure describe methods, apparatuses, and systems for hybrid low dropout regulator (LDO) architecture and realization to provide high power supply rejection ratio (PSRR) and high conversion efficiency (CE), and other benefits. The hybrid LDO may be coupled with dual rails for its analog LDO branch and digital LDO respectively to achieve high PSRR and high CE by utilizing the hybrid architecture with several feedback loops. Other embodiments may be described and claimed.