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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10840134 B1

PDFFull Text
Date of Patent:
Nov. 17, 2020

Filed:

Apr. 22, 2019

Interconnect structure and method

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chia-Cheng Chou, Keelung, TW;

Chih-Chien Chi, Hsinchu, TW;

Chung-Chi Ko, Nantou, TW;

Yao-Jen Chang, Taipei, TW;

Chen-Yuan Kao, Zhudong Township, TW;

Kai-Shiang Kuo, Hsinchu, TW;

Po-Cheng Shih, Hsinchu, TW;

Tze-Liang Lee, Hsinchu, TW;

Jun-yi Ruan, Taoyuan, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Thinh T Nguyen

Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 21/84 (2006.01); H01L 29/66 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76835 (2013.01); H01L 21/7684 (2013.01); H01L 21/76816 (2013.01); H01L 21/76826 (2013.01); H01L 21/76829 (2013.01); H01L 21/76843 (2013.01); H01L 21/76879 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 21/845 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53238 (2013.01); H01L 23/53295 (2013.01); H01L 29/66545 (2013.01); H01L 29/7851 (2013.01); H01L 21/76801 (2013.01); H01L 21/76807 (2013.01); H01L 21/76838 (2013.01); H01L 29/0847 (2013.01); H01L 2221/1047 (2013.01);
Abstract

A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

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