The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2020

Filed:

Dec. 20, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Gideon Gerzon, Zichron Yaakov, IL;

Dror Caspi, Kiryat Yam, IL;

Arie Aharon, Haifa, IL;

Ido Ouziel, Ein Carmel, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 9/30 (2018.01); G06F 12/0804 (2016.01);
U.S. Cl.
CPC ...
G06F 9/30101 (2013.01); G06F 9/30065 (2013.01); G06F 9/45558 (2013.01); G06F 12/0804 (2013.01); G06F 2009/45583 (2013.01); G06F 2212/1044 (2013.01);
Abstract

A processor includes a global register to store a value of an interrupted block count. A processor core, communicably coupled to the global register, may, upon execution of an instruction to flush blocks of a cache that are associated with a security domain: flush the blocks of the cache sequentially according to a flush loop of the cache; and in response to detection of a system interrupt: store a value of a current cache block count to the global register as the interrupted block count; and stop execution of the instruction to pause the flush of the blocks of the cache. After handling of the interrupt, the instruction may be called again to restart the flush of the cache.


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